Night Owl 6/Night Owl's Shareware - PDSI-006 - Night Owl Corp (1990).iso/016a/chips18b.zip/CHIPS.DOC

Text File | 1990-06-16 | 16KB | 387 lines

                CHIPS Version 1.8

             (c) 1990 William C. Parke

  CHIPS is an program designed to explore the hardware on an IBM PC
compatible.  It will make a series of tests to determine, as far as
possible, the kind of computer chips present in the particular machine.
These include the Central Processing Unit (CPU), the Numeric Data
Processor (NDP), and the various Asynchronous Communication Elements
(ACEs) used on the serial ports.  CHIPS demonstrates that software is
capable of checking detailed hardware capabilities directly. Programmers
can use more sophisticated coding when more advanced hardware is found.

  Run CHIPS with the DOS command:

   CHIPS

  To save a copy of the hardware configuration, use DOS redirection:

   CHIPS >chips.scn

  Although the hardware configuration of a computer can be verified by
internal visual inspection, it is not a particularly easy task.
Moreover, the critical question of whether the hardware will respond to
software can be at issue.  CHIPS uses software to make direct tests of
hardware elements.  It goes beyond the assumptions of the operating
system, whose configuration may be at variance with the actual
situation.  Thus, CHIPS will allow one to determine possible conflicts
between the hardware and the settings of the configuration DIP switches
on the motherboard of a PC or the CMOS memory in the AT computer.

        The CPU: Central Processing Unit

  Because of various quirks, design changes, and design improvements, it
is possible to distinguish between the following types of CPUs:

        8088    The original 8/16 bit Intel CPU used in the IBM PC
        8086    The full 16 bit version
        V20     NEC's clone of the 8088 with added 8080 mode
        V30     NEC's clone of the 8086 with added 8080 mode
        80188   An enhanced 8088 with expanded i/o instructions
        80186   An enhanced 8086 with expanded i/o instructions
        80286   The first micro CPU with protected mode
        80386   Extended with 32 bit registers, new instructions
        80486   Integrated with NDP, cache buffer, extended addressing

  For the 8088, CHIPS will test for a serious hardware bug in the early
production chips which could cause the computer to halt during a program
execution.  For the 80386, CHIPS looks for the infamous 'multiply bug'
in early production runs.  A double sigma (printed on the chip) means
the chip passed Intel's tests.  If CHIPS confirms this test, it will
print a double sigma after the chip name.

  CHIPS next determines the speed of the CPU and the number of effective
wait states currently used by the CPU in accessing memory.  These
are printed after the CPU identification.

        The Interrupt Controllers

  The orginal IBM PC used the Intel 8259 chip to manage the various
  hardware interrupts from the keyboard, drives, clock, ports, etc.  The
  AT machine cascaded the master 8259 with a slave 8259 controller,
  expanding the number of hardware interrupt lines from eight to
  fifteen.  CHIPS will report on the existence of one or both of
  these controllers.

        The NDP: Numeric Data coProcessor

  CHIPS will also test for the Numeric Data Processor (math coprocessor)
to see if it is available to accompany the CPU.  [Note: The NDP is
integrated into the 80486.]   Function and designed improvements in the
NDP allow software to distinguish between the following possibilities:

        no coprocessor
        8087    NDP to accompany the 8088/8086
        80287   NDP to accompany the 80286 or the 80386
        80387   NDP to accompany the 80386

        The ACEs: Asynchronous Communication Elements

  The serial ports on the IBM PC are controlled by an Intel 8250 or its
equivalent.  Most PCs have at least one 8250.  Some serial cards use a
faster version, the 16450 or the 16550.  A more advanced chip, the
16550AN, contains an internal 16 byte buffer, useful in multitasking
operations.  CHIPS can distinguish:

        no ACEs on any ports
        8250    Serial controllers
        16450   Serial controllers, extended version of the 8250
        16550   Serial controllers, faster version of the 8250
        16550AN Serial controllers, with FIFO buffer.

        The Parallel and Game Ports

  The IBM PC add-on cards generally do not use an intelligent chip to
control the printer ports or the game port.  Instead, these ports, when
available, are controlled by logic chips.  CHIPS will search for real
ports at the default locations.

        Display of IBM BIOS Assumptions for Attached Devices

  At boot time, the IBM PC and AT reads the user configuration settings
for various devices which may be attached to the system.  Some of this
information is stored in the BIOS (Basic Input/Output System) memory.
CHIPS will allow you to compare the actual hardware it found with the
settings recorded in the BIOS memory.  In the case of the NDP, CHIPS
shows the BIOS NDP-present flag (yes or no).  For the serial ports,
CHIPS will give the current name assigned by DOS to the ports used for
serial devices.  This assignment may vary, as it is can be changed using
various swapping or redirection utilities.  CHIPS reports the same kind
of information for the parallel (printer) ports.  After showing if the
game port is active, CHIPS gives the setting of the BIOS equipment flag
for this port.  A test is also made to see if a mouse driver has been
installed in the memory of the machine.

        Mouse Support

Chips can distinguish a serial, bus, and PS/2 mouse when a mouse
driver is present.

        Sound Support

Chips will test for a MIDI or AdLib port and accompanying driver.


        Example of CHIPS Display:

Chip Identification V1.8ß (c) William C. Parke 1990

 Central Processing Unit: -8088-- 8 MHz with 0 wait states.
     8088 interrupt test: Passed.
        Math coprocessor: -8087-- Present and flagged in BIOS.
   Interrupt Controllers: Master 8259 Found, Slave 8259 Not Found.
       Serial port  3F8H: -8250-- Active.
              port  2F8H: -8250-- Active.
              port  3E8H: Not Active.
              port  2E8H: Not Active.
     Parallel port  3BCH: ------- Active as LPT1:
              port  378H: ------- Active as LPT2:
              port  278H: Not Active.
         Game port  201H: Not Active and not flagged in BIOS.
       Sound I/O support: PC Speaker.
                   Mouse: No Driver Found.


Technical Details:

Distinguishing CPUs

    "8088 programmable registers and addressing modes are
    identical to the 8086 in every way.  Except for execution
    speed, to the programmer the 8088 is identical to the 8086."
    (Osborne/McGraw-Hill, Russell Rector and George Alexy, The
    8086 Book, 1980)

  A statement such as the above is a challenge to programmers!  The
second sentence turns out to be wrong.  There is a trivial software test
one can make to distinguish the 8088 from the 8086 (and the 80188 from
the 80186), despite the claims that the only difference between these
chips is the treatment of the external data hardware lines.

  The test in question takes advantage of the fact that the 8088 has
a 4-byte prefetch queue, while the 8086 has a 6-byte prefetch queue.
This means that these chips pull the next set of instructions to
be executed into an internal buffer.  Now suppose we instruct the CPU
to change one of the memory locations which had just been prefetched.
Then the code at that location will not be the same as the prefetched
code.  On the other hand, if the change is made to the code in memory
just out of reach of the 8088, but still within reach of the 8086
prefetch operations, these chips will execute different instructions.
For example,

                XOR     CX,CX
                CLI
                MOV     BYTE PTR [NEXT],NOP
                NOP
        NEXT:   INC     CX
                STI
                JCXZ    8088

will result in CX=1 on the 8086, but CX=0 on the 8088.

  The 80186 can be distinquished from the 8086 using a variety of
software differences.  One of the simplest is the shift operation.
Chips after the 8086 do not waste time bit shifting more than 32
times (the maximum size of any one register), so the shift value
(in the CL register) is truncated modulo 32 before the operation.
Thus:


        MOV     CL,33                   ; 8018x shifts modulo 32
        SHL     CL,CL
        JCXZ    8088

will result in a non-zero flag being set if the chip is above the 8088
generation, since only a single bit shift occurs in that case.

  The 8088 and 8086 differ from the 80286 and later chips in how they
handle the value of the stack pointer when it is pushed onto the
stack:

                PUSH    SP
                POP     AX
                CMP     AX,SP
                JNZ     8088

After the above operation, AX will contain the value of the stack pointer
before the push if the chip is an 80286 or later.

  The V20/V30 chips can be detected by executing extended V20 code which
also is meaningful on the 8088.  For example,

                SET1    CX,0            ; v20 code

sets a bit in the CX register.  On the 8088 this code is

                POP     CS
                SBB     AX,0C1H

which does not affect the CX register.  However, this code must be avoided
on an 80386 machine, which can lock at the POP CS.  A simpler test
is the following:

                XOR     AL,AL
                MOV     AL,40H
                MUL     AL
                JZ      NEC

since the 8088 will set NZ on multiply while the NEC does not.

  The 80386 handles more flag register bits than the 80286.  By trying
to set the upper four bits of the flag register and then testing:

                MOV     AX,0F000H
                PUSH    AX
                POPF
                PUSHF
                POP     AX
                AND     AX,0F000H
                JZ      80286

the upper four bits will be reset on chips below the 80386.

  The 80486 can be distinquished from the 80386 by the fact that its
prefetch queue is 32 bytes in size instead of 16 bytes.  The test
code is similar to that above which separates the 8088 from the
8086, except one needs 15 nops instead of one.  Alternatively, one
can attempt to set the 29th bit of the CR0 register (cache write-through
bit), which cannot be set on the 80386:

        MOV     EAX,CR0         ; 0FH,20H,0C0H
        MOV     EBX,EAX         ; 66H,8BH,0D8H
        XOR     EAX,20000000H   ; 66H,35H,00H,00H,00H,20H
        MOV     CR0,EAX         ; 0FH,22H,0C0H
        MOV     EAX,CR0         ; 0FH,20H,0C0H
        CMP     EAX,EBX         ; 66H,3BH,0C3H
        JZ      80386

CPU speed tests are made by timing repeated CPU divide instructions.

Wait states are extimated by the time required to make repeated
memory-to-memory moves.


Finding the Numeric Data coProcessor:


   Attempting to execute commands designed for the math coprocessor
on a system without one is a delicate matter.  Some instructions
will cause particular CPUs to lock up.  (Unfortunately, FSTENV, which
could be used to save the current state of the coprocessor, freezes
PS/2-55 80386SX machines).  Others require the CPU to wait for the
coprocessor to finish its task before continuing.  Assemblers and
compilers often insert the WAIT instruction in such cases.  However,
asking a CPU to WAIT when there is no coprocessor is asking it to wait
forever.  It appears that

        FINIT                   ; initialize coprocessor
        JMP $+2
        JMP $+2
        JMP $+2                 ; imitate a wait
        FSTCW WORD PTR NDPCW    ; store NDP control word
        MOV AX,WORD PTR NDPCW
        AND AH,11111B           ; isolate inf,rounding,precision bits
        CMP AH,,00011B
        JZ GOT_NDP

will pass through the digestive tracks of the 80x86 series without
blockage, even when no coprocessor is connected.  When there is a
coprocessor, the control word bits 8-12 will be set to indicate the
default 64 bit precision, nearest rounding, and projective infinity.

  To differentiate an 8087 from an 80287 or later, one can drop the
interrupt-enable-mask bit of the control register, disable interrupts,
read the register back, and check if the mask bit is still 0 (interrupts
still enabled):

        AND     WORD PTR NDPCW,0FF7FH    ; drop bit 7 IEM inter enable mask
        FLDCW   WORD PTR NDPCW           ; load control word into NDP
        FDISI                            ; disable interrupts (ignored on 287)
        FSTCW   WORD PTR NDPCW           ; store control word in memory
        TEST    WORD PTR NDPCW,80H       ; is IEM of control word back again?
        JNZ     80287

The 80387 will reset the zero flag bit in its status register on
initialization, but the 80287 will not:

        FLDZ                            ; zero st(0)
        FXAM                            ; set status flags
        FINIT                           ; reset 80x87
        FSTSW   WORD PTR NDPSW          ; get status word
        TEST    BYTE PTR NDPSW+1,01000000B      ; check C3 = ZF
        JNZ     80287                   ; 80287 does not reset ZF


Testing for Real Serial Ports:

   A relatively straight foward test can determine if the standard
serial ports have an active chip controlling them.  For example, reading
in the line-control register, reversing its first six bits, sending the
reversed set out, reading it back in, then checking if the new bits
are as they were sent out.  Of course, this testing should be done
with interrupts turned off, and the original register value restored
before turning them back on:

        MOV     DX,3FCH         ; first serial port + 2
        IN      AL,DX           ; get line control reg
        MOV     BL,AL           ; save
        CLI
        XOR     AL,0111111B     ; reverse bits
        MOV     BH,AL           ; save reversed value
        OUT     DX,AL
        JMP     $+2
        IN      AL,DX
        MOV     AH,AL           ; save read value
        MOV     AL,BL           ; get original line control
        OUT     DX,AL           ; restore original
        STI
        CMP     AH,BH           ; see if it changed
        JZ      GOT_COM

The 16450 chips has an additional eighth read/write port, which
can be tested for.

To tell if one of the newer 16550 or 16550AN chips is present,
one can use the two new bits (6-7) in the interrupt-identification
register.  These bits, when set, clear and enable the FIFO internal
receive buffer.  These chips are distinquishable by whether these
bits can be set:
                bits 7  6
                     0  0   8250 ACE
                     0  1   unknown
                     1  0   16550
                     1  1   16550AN


Parallel Port Testing:

  A live parallel port can have its interrupt-enable bit set at the
control register port.  Testing if this bit can be toggled serves as an
appropriate probe.  The testing must be done with software interrupts
turned off as there may not be any interrupt handler for the parallel
port.  (Moreover, the original IBM PC had a hardware fault which
prevented proper parallel port interrupt handling.)

Mouse Presence:

  There is no standard mouse port on the IBM PC.  One can operate a
mouse from a serial port, a bus card, or through the PS/2 keyboard
controller.

  CHIPS can look for a mouse driver interface in software.  If the
driver is present, there is a very good chance the system has the
necessary hardware for a mouse.  CHIPS attempts to find if the mouse
driver has taken over a serial port interrupt.  It will look at
the keyboard controller for a PS/2 mouse.

Sound Ports:

  The MIDI-401 (musical instrument digital interface) takes the ports
330H and 331H.  CHIPS tries to get an acknowledgement to a status read
of a possible MIDI card.  An AdLib music card uses the port 388H.  CHIPS
attempts to initialize the AdLib music card.  If successful, it will
look for an AdLib driver, which uses interrupt 65h.